Technical Field
The present invention relates to semiconductor devices and processing methods, and more particularly to improved dielectric fill processes especially with components with small gaps between them.
Description of the Related Art
Semiconductor devices include a wide range of topographical features. In some devices, high aspect ratio features cause deep and narrow gaps to form between them. The gaps are often filled with a dielectric fill process. The dielectric fill process often fills the gaps from the bottom up. As material is deposited in the bottom of the gap, material begins to form on sidewalls of the features as well. This can cause pinch off and result in voids.
Scaling a pitch of features (e.g., making device sizes smaller) can lead to issues during the fill process and during process steps that recess the fill material to expose more of the features. In one example, the features may include gate structures with dielectric spacers and hard mask caps. During a fill process or a recess process, voids can form and hard mask or spacer damage can occur. This may result in issues with these structures later on in the process or with the reliability of the device after manufacture.